1. Field of the Invention
The present invention relates generally to methods for forming semiconductor devices and, more particularly, to methods for forming planarized multilevel metallization in an integrated circuit.
2. Description of Related Art
Over the past several years, rapid progress has been made in the semiconductor industry. For example, more electronic components can now be integrated on a single chip to increase performance, reduce cost, and improve process reliability. As a consequence, the interconnect structures by which the electronic components are connected are more complicated.
Interconnect technology, i.e., creating connections between conducting regions, relies heavily upon planarization techniques. Typically, the conductive regions are made of aluminum (Al), which is an attractive material for integrated circuit metallization due to its high conductivity and low cost. The processing required to form aluminum metallization is also relatively easy, as it can be readily evaporated or sputtered onto a wafer. However, certain drawbacks do exist for aluminum metallization such as its relatively poor step coverage, misalignments, and stress-induced issues such as voids. For example, mechanical stress in aluminum material can cause voids therein. Step-coverage faults and stress-induced voids can cause a misalignment and/or opening in a metal line or contact.
As circuit density and device performance requirements increase, more complex wiring or routing of interconnects between conducting regions is required. Vertical and horizontal interconnects are needed as the number of metallization layers increases to meet the requirements of more complex circuits. Present-generation devices may require up to, for example, 5 or 6 layers of metallization to meet the wiring needs of state-of-the-art integrated circuits such as logic devices and static random access memories (SRAMs). Vertical interconnect structures are typically formed using mask-etching processes wherein via are generated over and on metallic lines.
FIG. 1 illustrates a result of an early stage of such a prior-art fabrication process. The illustrated example comprises a substrate 35, an inter-layer dielectric (ILD) layer 36 that overlies the substrate 35, and a metal layer 38 formed of aluminum (Al) on the ILD layer 36. A relatively thin layer 39a of titanium (Ti) is formed on the metal layer 38, and a likewise relatively thin layer 39b of titanium nitride (TiN) is formed on the Ti layer. The Ti and TiN layers form an anti-reflective coating (ARC) 39 of Ti/TiN. A silicon oxynitride (SiON) layer is formed on the ARC 39 to form stack layers, and the stack layers can be etched back to form lines. Subsequently, a high density plasma (HDP) layer can be deposited, followed by the application and patterning of a photoresist to facilitate formation of via by etching the HDP deposited layer and the SiON layer. The photoresist can then be removed, and the via can be filled with a via filler such as tungsten to thereby form a contact.
Circuit structures of the type just described are formed through a photolithography process using a first reticle mask. Photo misalignment errors can occur, for example, when a second reticle mask has not been properly aligned with a first circuit structure. More to the point, photo misalignment can occur when there is a stress-induced shift in a metal film deposition after a photolithography exposure. The stress-induced shift may create an asymmetric metal profile because of the relatively high stress of, for example, a Ti/TiN layer such as ARC 39 above aluminum metal layer 38 in FIG. 1. Metal stress can cause a shift of an alignment mark, resulting in misalignment between a metal layer and a contact element. The term “metal stress” refers to flexing of a metal layer as heat is applied, due, for example, to differences in thermal rates of expansion associated with different metals and different materials. The intrinsic metal stress of, for example, TiN may further exacerbate step coverage asymmetry problems. Such asymmetry problems may occur, for example, when one side of a contact feature sees more deposition flux than another side. Asymmetry can be more prevalent on the outer edges of a wafer when compared to asymmetry near its center.
A need exists in the prior art to reduce metal stress, reduce photo misalignment, improve metal step coverage, and improve process reliability of semiconductor devices. A further need exists to develop optimal methods for forming planarized multilevel metallization in semiconductor devices, for example, integrated circuits.